Advanced Embedded Packaging Technology

This exhibit integrates advanced embedded packaging, a Power SiP architecture, and the development results of a 1.2 kV half-bridge chip-embedded power module for highly integrated E-axle applications. The prototype demonstrates up to 80% module volume reduction, 40% lower parasitic inductance, and 10% higher power density. Under forced-air cooling, the chip-to-case thermal resistance remains below 0.267 °C/W, showing strong electrical, thermal, and manufacturing potential.